Weiwei Shan

发布者:陈国华发布时间:2014-10-26浏览次数:2301

Basic Information
Weiwei Shan


Tel:86-25-83793265 ext.8506


Email:wwshan@seu.edu.cn


Address:North 5th floor, Yifu Science & Technology Hall, ,SEU,2 Sipailou, Nanjing
 
Research Interest

Research interest mainly focuses on:
(1) Low power integrated circuit design, including on-chip timing monitor based adaptive voltage scaling, near sub-threshold integrated circuit design, wide operating VLSI design;
(2) Digital logic design and verification, reconfigurable computing and information security circuit design.

Recent Research Projects:
(1) National Natural Science Foundation of China (Grant No. 61574033), ' PVT resilient design methodology of near threshold ultra wide range voltage IC', 2016.1-2019.12, PI, ¥680,400.
(2)National High Technology Research and Development Program of China (863 Project), 'Energy efficient integrated circuit design key technologies', 2015.1-2017.12, ¥23,010,000, collaborating with Tsinghua University, Fudan University, Peking University and Beijing Huada company.
(3)National Natural Science Foundation of China (Grant No. 61006029), 'Research of ultra dynamic voltage scaling for low power SoC', 2011.1-2013.12, PI, ¥200,000.
(4)Natural Science Foundation of Jiangsu province, China (Grant No. BK2010165), 'SoC ultra low power technologies and power emulator design', 2010.7-2012.12, PI, ¥100,000.
(5)National High Technology Research and Development Program of China (863 Project), 'Embedded reconfigurable mobile media processing technologies'. 2009.1-2012.6, ¥5,350,000.
(6)Open Research funding of State Key Laboratory of ASIC and System, Fudan University (2015KF010), 'Adaptive voltage and frequency scaling technologies for energy efficient processor'. 2015.1-2016.12, PI,  ¥50,000.                  

 
Biographical Information

1999.9-2003.6 Bachelor in Microelectronics from Tianjin University;
2003.9-2009.1 Ph.D. in Microelectronics from Tsinghua University;
2007.8-2008.8 Visiting scholar in ECE department, University of Maryland, College Park;
2009.2-2012.3 Lecturer in School of Electronic Science & Engineering, Southeast University;
2012.4-Now Associate professor in School of Electronic Science & Engineering, Southeast University.

 
Selected Publications

1.Weiwei Shan, Xingyuan Fu and Zhipeng Xu, A Secure Reconfigurable Crypto IC with Countermeasures against SPA, DPA and EMA, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 34, Issue: 7, pp. 1201 - 1205, 2015.7
2.Weiwei Shan, Haolin Gu, Bo Li, Xiaoqing Wu, Haikun Jin, Yintao Guo and Peng Cao, An improved timing monitor for deep dynamic voltage scaling system, IEICE Electronics Express, Vol.10.no.6, pp. 1-7, 2013.3
3.Weiwei Shan, Longxing Shi, Xingyuan Fu, Chaoxuan Tian, Xiao Zhang, Zhipeng Xu, and Jun Yang, A Side-channel Analysis Resistant Reconfigurable Cryptographic Coprocessor Supporting Multiple Block Cipher Algorithms, 51st Design Automation Conference (DAC), 2014.6  
4.Weiwei Shan, Xin Chen, Bo Li, Peng Cao, Jie Li, Gugang Gao and Longxing Shi, Evaluation of Correlation Power Analysis Resistance and Its Application on Asymmetric Mask Protected Data Encryption Standard Hardware, IEEE transaction on Instrumentation and Measurement, Volume: 62, Issue: 10, pp. 2716 – 2724, 2013.10
5.Weiwei Shan and Zhipeng Xu, Timing Error Prediction based Adaptive Voltage Scaling for Dynamic Variation Tolerance, 2014 IEEE Asia Pacific Conference on Circuit and Systems, (APCCAS) (Invited paper & talk), pp. 739-742, Japan, 2014.11
6.Shuai Shao, Youhua Shi, Wentao Dai, Jianyi Meng and Weiwei Shan, A universal delay line circuit for variation resilient IC with self-calibrated time-to-digital converter, EDSSC 2015, IEEE Conference on Electron Devices and Solid-State Circuits, Singapore, June 1-4, 2015,
7.Weiwei Shan, Yuan Ma, Robert W. Newcomb and Dongming Jin. Analog Circuit Implementation of a Variable Universe Adaptive Fuzzy Logic Controller. IEEE Transactions on Circuit and Systems II: Brief Paper, 2008, 55(10): 976-980
8.Weiwei Shan, Xiao Zhang, Xingyuan Fu and Peng Cao, VLSI Design of a Reconfigurable S-box Based on Memory Sharing Method, IEICE Electronics Express, Vol. 11 No. 1, pp. 1-6, 2014.1.
9.Weiwei Shan, Liang yan and Dong-ming Jin, 'CMOS circuit design of a Takagi-Sugeno fuzzy logic controller', Journal of Circuits, Systems, and Computers, Vol. 18 No. 4 , June 2009, pp. 841-856
10.Weiwei Shan and Xin Chen, A novel combined proportional-derivative control for electrostatic MEMS mirror actuation,IEICE TRANS. ELECTRON. Vol. E94C, No.9. pp. 1486-1489, 2011.9
11.Weiwei Shan, Xiqun Zhu and Yuan Ma, 'Adaptive Fuzzy Logic Controller and Its Application in MEMS Mirror Actuation Feedback Control', Lecture Notes in Computer Science, Vol. 5788, pp. 74-81, 2009  
12.Weiwei Shan, Yinchao Lu, Huafang Sun and Junyin Liu, 'A Novel Analog Circuit Design and Test of a Triangular Membership Function', Electronics and Signal Processing - Selected Papers from the 2011 International Conference on Electric and Electronics, EEIC 2011
13.Weiwei Shan, Dongming Jin, Weiwei Jin, et al. VLSI Implementation of a Self-tuning Fuzzy Controller Based on Variable Universe of Discourse,Lecture notes in Computer Science, 2005, vol:3613(2005): pp:1044 -1052
14.Weiwei Shan, Weizhi Wang and Dongming Jin, Analog circuit on CMOS for low power fuzzy logic controller, Tsinghua Science and Technology, Vol.48(7), Jul. 2008 , p 1198-1201
15.Zhikuang Cai, Haobo Xu, Shixuan Que, Weiwei Shan, and Jun Yang, On chip long-term jitter measurement for PLL based undersample technique, IEICE Electronics Express, Vol.10.no.24, pp. 1-9, 2013.12
16. Zhikuang Cai, WeiWei Shan and Jie Li A Novel Hybrid Fuzzification Method for Fuzzy Logic Controller and Its Circuit Implementation, Chinese Journal of Electronics Vol.22, No.1, Jan. 2013, pp. 67-70
17.Xin Chen, Ning Wu, Wei Hu and Weiwei Shan, BIST design of power switch, IEICE ELECTRONICS EXPRESS, Vol.10.no.15, pp.1-5 , 2013.8   

Selected Patents
1.Dynamic Voltage Scaling System based on On-Chip Monitoring and Voltage Prediction, United States Patent, Patent NO.: US 8,909,999 B2, Dec. 9, 2014.
2.Power-On-Reset (POR) Circuit with Zero Steady-state Current Consumption and Stable Pull-Up Voltage, United States Patent, Patent NO.: US 8, 803, 580 B2, Aug. 12, 2014
3.A timing error recovery circuit for CPU pipeline, Chinese invention patent, Patent NO.: ZL201210574735.6, 2015.7.
4.A dynamic voltage scaling system for low power application, Chinese invention patent, Patent NO.: ZL201010547625.1, 2014.8.
5.A reconfigurable S-box based on RAM-sharing technique, Chinese invention patent, Patent NO.: ZL201110284750.2, 2014.9.
6.A reconfigurable cipher coprocessor and its countermeasure methods for power analysis, Chinese invention patent, Patent NO.: ZL201110302279.5, 2014.11.
7.An on-chip timing monitor circuit for dynamic voltage scaling system, Chinese invention patent, Patent NO.: ZL201110446350.7, 2013.10.